The present invention relates to semiconductor devices and more particularly to power semiconductor switching devices.
It is well known that in a conventional power semiconductor switching device there is a trade off between the ON resistance the device and its ability to withstand breakdown under reverse voltage conditions. In a conventional device, the breakdown voltage withstand capability is supported by a PN junction. Thus, designers often have to select a resistivity for the P region (e.g. base region) and a resistivity for the N region (e.g. drift region) to obtain a desired combination of the breakdown voltage and ON resistance.
According to the well known superjunction principles, the drift region of the device, which contributes significantly to the ON resistance of the device, is provided with charge compensation regions to deplete the drift region under reverse voltage. As a result, the drift region can be designed more conductive with less concern for a tradeoff with the breakdown voltage capability. One known method for fabricating a superjunction device is to implant dopants into the drift region to obtain the charge compensation regions. Such a method, however, requires annealing and the like steps after implanting, which is not desirable specially when the device is formed using III-nitride materials.
U.S. patent application Ser. No. 11/004,189, assigned to the assignee of the present application, discloses a device and method for fabricating a superjunction device in which the charge compensation regions are grown epitaxially rather than implanting to form the charge compensation regions.
A device according to the present invention includes charge compensation regions epitaxially formed according to the method disclosed in U.S. patent application Ser. No. 11/004,189, and additional beneficial features.
Specifically, a device according to the present invention includes a substrate, common conduction regions of a first conductivity disposed on the substrate, charge compensation regions of a second conductivity each adjacent a respective common conduction region, a stand off region of the first conductivity over the common conduction regions and the charge compensation regions, a base region of the second conductivity over the stand off region, a source region of the first conductivity over the base region, a gate trench extending through the source region and the base region, a gate insulation body lining the sidewalls of the gate trench, a gate electrode inside the trench, a source electrode ohmically connected to the source region, and a drain electrode ohmically connected to the substrate.
According to one aspect of the present invention, each charge compensation region is disposed over a respective pillar of a growth inhibition material.
According to another aspect of the present invention, the common conduction regions, the charge compensation regions, the stand off region, the base region and the source regions are comprised of a respective III-nitride material.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.